The present invention relates to a semiconductor memory device, particularly to a circuit sensing voltage level on a bit line in the semiconductor memory device.
Prior art semiconductor memory device designs reduce bit-line sensing noise by dividing the memory cell array into several blocks, for example four memory cell array blocks BLK1, BLK2, BLK3 and BLK4 as shown in FIG. 1, or by decreasing the mutual capacitance between one bit line and another one. The sensing operations of bit lines in a dynamic random access memory (DRAM) is made to all of selected bit lines, even if divided into blocks, at the same time. In other devices, such as field memory (or frame memory) or DRAM-equipped application specific integrated circuits (ASIC), the sensing operation can be provided to each one of the memory cell array blocks at different times, due to sufficient row access time, and so disperse noise and peak current.
FIG. 2 illustrates a well known DRAM column circuitry, which includes a memory cell 21, a sense amplifier 22 and an equalizing circuit 26. Sense amplifier 22 consists of n-type MOS transistors 23, 24 and 25 and p-type MOS transistors 27 and 28, which together amplify and develops the voltage difference between bit lines BL and BLB after a word line WL is activated to select a memory cell 21. Memory cell selection is controlled by sensing signals LA and LSAEG. Equalizing circuit 26, which consists of n-type MOS transistors 29, 31 and 32, pre-charges and equalizes both bit lines with equalizing voltage VBL before and after a read or write operation of DRAM, being controlled by equalizing signal .phi.EQ.
FIG. 3 shows a block diagram of a conventional bit-line sensing control circuit, consisting of an enable clock generator 10, a word-line enable circuit 30, a bit-line sensing enable circuit 50 and a bit-line sensing driver 70. The enable clock generator 10 generates an initial activating clock .phi.1 after receiving an address informing signal LXE, which is obtained when the external address becomes valid. The external address becomes valid when the row address strobe signal ( RAS )transitions to the logic state "low", and after the initial activating clock .phi.1, the a word-line enable circuit 30 generates makes word-line enable signal .phi.X1. Then the bit-line sensing enable circuit 50 generates a bit-line sensing enable signal .phi.S1 and as a result, p- type and n-type sensing signals LA1 and LSAEG1, respectively, are generated from the bit-line sensing driver 70, which receives the bit-line sensing enable signal .phi.S1. The sensing signals are then applied to the sense amplifiers 22 of FIG. 1. The number of sense amplifiers corresponds to the number of columns in the memory cell array blocks, such as blocks BLK1, BLK2, BLK3 and BLK4 as illustrated in FIG. 1.
Since, however, one of the sense amplifiers embedded in each one of the memory cell array blocks is put into the simultaneous sensing operation together with sense amplifiers belonging to other memory cell array blocks, selected pairs of bit lines are simultaneously developed, the bit line BL going to "high" or "low" level while the bit-line BL to "low" or "high" level. It is, also, well known that a noise such as spike currents may be generated during the bit-line sensing operation because of large bit-line voltage swings between power supply voltage and ground voltage. Therefore, in the conventional scheme in which all bit lines are simultaneously sensed in each of the memory cell array blocks, the sensing noises due to spike currents that may occur at the same time can result in faulty memory operation.